CAST, Inc.

06/08/2026

CAN networks have evolved significantly over the past two decades. As vehicles become increasingly connected, functional safety and cybersecurity requirements continue to grow. Our latest white paper explores how CAN XL builds on the proven foundations of Classical CAN and CAN FD while introducing new capabilities for next-generation vehicle architectures.

Read the white paper: https://www.cast-inc.com/blog/classical-can-and-can-fd-can-xl-functional-safety-and-security-next-generation-vehicle

06/05/2026

As vehicle and industrial networks grow in complexity, engineers must address both functional safety and cybersecurity requirements without sacrificing performance.

In this video, we explore how CAN XL supports functional safety, the role of controller hardware and higher-layer protocols, and how CANsec provides authentication and encryption with minimal network overhead.

https://www.youtube.com/watch?v=Co_LV525KgQ

CAN XL is designed to meet the growing demands of modern automotive...

06/03/2026

As AI, HPC, datacenter, and scientific applications generate ever-larger datasets, moving, storing, and processing data efficiently has become a growing challenge. The wrong compression choice can lead to wasted bandwidth, increased storage costs, or performance bottlenecks.

So how do you determine which lossless compression algorithm is right for your application?

This white paper provides a detailed comparison of GZIP, ZSTD, LZ4, and Snappy, examining the trade-offs between compression ratio, throughput, latency, and hardware implementation requirements. Whether you're designing FPGA- or ASIC-based systems, it offers practical guidance for selecting the right compression solution.

A good place to start if you missed our last presentation.

Read the white paper: https://www.cast-inc.com/blog/white-paper-evaluating-lossless-data-compression-algorithms-and-cores

05/29/2026

Thank you to everyone who attended our presentation, "Accelerating Data: Lossless Compression for HPC, Datacenter, AI, and Scientific Data Pipelines," at the 3rd FPGA Developers' Forum at CERN.

The session explored how hardware-based lossless compression can help reduce bandwidth, memory, and storage demands in data-intensive systems while maintaining full data integrity. We discussed FPGA and ASIC implementations of LZ4, Snappy, GZIP/DEFLATE/Zlib, and Zstandard compression architectures and their trade-offs in throughput, compression ratio, and resource utilization.

We appreciate the insightful discussions, thoughtful questions, and the opportunity to connect with engineers, researchers, and FPGA developers from around the world. Thank you to CERN and the FPGA Developers' Forum organizers for hosting a great event.

Missed the presentation or would like to watch it again? The webcast replay will be available here: https://live.cern/event/i1549296/cdn

05/26/2026

Happening this week at the FPGA Developers’ Forum.

Join CAST’s Dr. Calliope-Louisa Sotiropoulou for a presentation on:

“Accelerating Data: Lossless Compression for HPC, Datacenter, AI, and Scientific Data Pipelines”

Learn how hardware-based lossless compression can improve bandwidth efficiency, throughput, and data movement performance in HPC, AI, and scientific computing applications.

May 28, 2026
14:05 CET
CERN – Main Auditorium
Webcast Link: https://live.cern/event/i1549296

05/18/2026

CAST’s configurable xSPI Memory Controller IP core continues to gain attention for helping SoC designers integrate high-performance serial memories with flexibility and functional safety support.

The article highlights:

- Support for xSPI, HyperBus™, and Xccela™ memories

- FuSa-ready configurations from ASIL-B through ASIL-D

- Fully synthesizable soft PHY for ASIC and FPGA portability

- Runtime configurability with automatic memory-device detection

- Support for single, dual, quad, octal, and 16x SPI interfaces

Read the full article]on SemiWiki: https://semiwiki.com/ip/cast/369140-configurable-xspi-memory-controller-ip-core-is-fusa-ready/

CAST's xSPI-MC memory controller IP supports adding serial flash and serial PSRAM to many applications, including ISO 26262 automotive...

05/14/2026

Enable deterministic real-time Ethernet communication with CAST’s TSN IP Core portfolio for ASIC and FPGA designs.

CAST offers a broad range of configurable TSN solutions including:

- TSN Ethernet Endpoint up to 10G for star network topologies

- TSN Ethernet Switched Endpoint for daisy-chained networks

- TSN Ethernet Switch for cut-through, ultra-low latency operation

Designed for automotive, industrial automation, robotics, aerospace, and embedded networking applications requiring precise synchronization and reliable low-latency communication.

Explore CAST TSN solutions: https://www.cast-inc.com/interfaces/automotive-bus-controllers

05/12/2026

CAST offers a broad portfolio of Audio Interface IP Cores for ASIC and FPGA designs, helping engineers integrate configurable and production-proven audio functionality with lower risk and faster development cycles.

From AC’97 control and asynchronous sample rate conversion to multichannel I2S/TDM transport and PDM-to-PCM conversion, CAST’s audio IP solutions support a wide range of embedded, industrial, automotive, and consumer applications.

Learn More: https://www.cast-inc.com/interfaces/audio

04/29/2026

Data movement is now one of the biggest performance limits in HPC, AI clusters, datacenters, and scientific systems. Learn how hardware-based lossless compression helps reduce bandwidth, memory, and storage demands while preserving full data accuracy.

See Calliope-Louisa Sotiropoulou, PhD, presentation at the FPGA Developers' Forum. Discover trade-offs between LZ4, Snappy, GZIP/DEFLATE/Zlib, and Zstandard for FPGA and ASIC designs.

Accelerating Data: Lossless Compression for HPC, Datacenter, AI, and Scientific Data Pipelines.

May 28, 2026 | 14:05 CET | Duration 30 minutes
Webcast Link: https://live.cern/event/i1549296

04/27/2026

CAST introduces MAC-SEC-MG, a MACsec protocol engine IP core for adding IEEE 802.1AE security to 1G, 10G, and higher-speed Ethernet SoCs.

Designed for ASIC and FPGA implementations, it enables high-throughput secure links with low latency, efficient resource use, and straightforward integration through standard interfaces.

A practical way to accelerate secure Ethernet development without adding software overhead.

Read more: https://www.cast-inc.com/press-releases/cast-introduces-mac-sec-mg-ip-core-secure-10g-ethernet-soc-designs