08/08/2019
DDR5 is Coming
DRAM chips are prevalent as the main memory in many computing devices – home and office computers, servers and mobile devices.
Double Data Rate 5 (DDR5) is the next-generation standard for random-access memory (RAM). The JEDEC DDR5 standard is currently in development with JEDEC's JC-42 Committee for Solid State Memories. However, some companies are planning to bring the first products to market by the end of 2019.
DDR5 will offer improved performance with greater power efficiency as compared to previous generation DRAM technologies. As planned, DDR5 will provide double the bandwidth and density over DDR4, along with delivering improved channel efficiency and lower power draw.
These enhancements, combined with a more user-friendly interface for server and client platforms, should allow for larger memory modules in smaller form-factor systems.
Support for these greater capacities will be dependent on the CPUs and chipsets that can take advantage of it. The data rate increase alone should more than keep up with potential future processors as the number of cores expands. For example, with its upcoming third-generation Ryzen processors, AMD has increased the core count to 16 cores in its high-end product. In response, Intel also has upped the number of cores for its own processors; the Intel Core i9-9900K processor, to cite just one example, packs eight cores.
Initially, DDR5 chips are expected to ship with a bandwidth of 4,800 MT/s, or about 1.9x that of DDR4 RAM. The official upper limit for the DDR5 RAM standard is 6,400 MT/s.
As it stands, perhaps the most important facet of DDR5 is that it requires comparatively less power to operate than previous generations of system memory. As such, DDR5 is expected to be utilized in mobile devices as well as in desktop and laptop PCs. Mainstream adoption is still more than a year away, but analysts expect DDR5 to make up 25 percent of the memory market by 2021 and 44 percent in 2022.
Low-Power DRAM
Earlier this year, JEDEC announced the publication of JESD209-5, “Low Power Double Data Rate 5” (LPDDR5). The LPDDR5 standard is an industry-leading low-power volatile DRAM device memory standard for storage of system code, software applications and user data.
LPDDR5 will eventually operate at an I/O rate of 6,400 MT/s, 50 percent higher than that of the first version of LPDDR4. This will significantly boost memory speed and efficiency for a variety of applications, including mobile computing devices such as smartphones, tablets and thin notebooks.
In addition, LPDDR5 offers new features designed for mission critical applications. To address the need for data reliability in automotive applications, LPDDR5 introduces the support of Error Correcting Code (ECC) on the interface between the SoC and DRAM.
ECC is an established memory technology used in a large array of applications to increase reliability. Through the use of ECC, single-bit errors are detected and corrected automatically providing higher memory reliability. ECC benefits all usage modes and provides better mobile power efficiency.
LPDDR5 features two new operations, Data-Copy and Write-X, focused on improving power consumption. The Data-Copy command instructs the device to copy data transmitted on a single I/O pin to other I/O pins, eliminating the need to transmit data to these pins. Write-X eliminates the need to send data from the SoC to the LPDDR5 device when transferring data. Reducing data transmission with these new commands will help reduce overall system power consumption.
Expect to see LPDDR5 memory chips in phones by next spring.