TESDA : Taiwan Electronic System Design Automation

03/06/2025

𝗙𝘂𝗻 𝗙𝗮𝗰𝘁:
More than 70% of SoC errors are caught after verification at the IP level is complete. Such issues occur when all IPs and subsystems are integrated, partly because the problems are unclear during development. Because of this, system-level errors are often found during SoC-level verification.

29/05/2025

Wishing everyone a joyful and peaceful Dragon Boat Festival! 🐉🥟

23/05/2025

🧠 𝗪𝗵𝘆 𝘁𝗵𝗲 𝗖𝗼𝗻𝘃𝗲𝗻𝘁𝗶𝗼𝗻𝗮𝗹 𝗩𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻 𝗖𝗮𝗻𝗻𝗼𝘁 𝗦𝗰𝗮𝗹𝗲 𝗳𝗼𝗿 𝗔𝗜 𝗦𝗼𝗖𝘀 𝗮𝗻𝘆𝗺𝗼𝗿𝗲

As AI chips become more complex, contemporary RTL-centric verification streams are finding it hard to cope. Here's why:

🔹 1. Massive Parallelism, Massive Headaches
AI SoCs are typically seen as having a complex of compute engines, accelerators, and memory controllers that operate in parallel. Since verifying interactions at the RTL is excruciatingly slow and fails to detect system-level bugs that arise once elements are fully assembled.

🔹 2. Time-to-Market Pressure
For the AI hardware race, the teams cannot wait or delay their production for 6–12 months before validating each IP block, before finding the system-level behavior. Waiting for RTL to catch architectural issues is no longer an option.

🔹 3. Late Bugs Discovery = Expensive Fixes
The longer the bug is discovered during the flow, the more expensive it will be to fix. Because of their interdependencies, AI chips are also more susceptible to architectural misalignments that appear late, unless checked prematurely at the subsystem level.

🔹 4. The Data Movement Bottleneck
In AI SoCs, the data locality and the bandwidth are the key parameters for performance. Traditional flows tend to be neglective of verification of interconnect behavior, memory bottlenecks, and data reuse patterns at the system level.

🔹 5. More Than RTL is Required for Software-Driven Validation.
AI workloads, Software interaction verification at the RTL stage is too late. At an architectural level, it will be better if the verification teams check the system behavior and scheduling decisions in advance, even before RTL is ready.

👉 Is your team still trapped in the traditional flows?
Discuss with TESDA how architectural-level verification can be of help in scaling.

15/05/2025

𝗦𝘂𝗯𝘀𝘆𝘀𝘁𝗲𝗺 𝗩𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻: 𝗜𝘁𝘀 𝗥𝗼𝗹𝗲 𝗶𝗻 𝗔𝗱𝗱𝗿𝗲𝘀𝘀𝗶𝗻𝗴 𝗖𝗵𝗮𝗹𝗹𝗲𝗻𝗴𝗲𝘀 𝗶𝗻 𝗦𝗼𝗖 𝗗𝗲𝘃𝗲𝗹𝗼𝗽𝗺𝗲𝗻𝘁 𝗣𝗿𝗼𝗰𝗲𝘀𝘀𝗲𝘀



As SoC designs become more complex, the effort to verify the whole chip requires exponentially more time than before and introduces many potential problems. It is why subsystem verification is important.



To get around the wait for a full SoC, engineers verify subsystems, their smaller, special-purpose blocks, themselves. This verification approach tests subsystems such as a processor cluster, memory controller, and communication interface. Early verification of subsystems enables the engineers to find the issues earlier, decrease the debugging time, and enable reusing these elements in various SoC design solutions.



Using automated testbenches in the design of subsystems aids teams in detecting issues earlier and simplifying the last phase of SoC integration. Subsystem verification transcends technical protocols and gives teams a practice method of dealing with complex SoC projects more smoothly.

With the "divide and conquer" approach, TESDA teams divide an SoC into manageable chunks of subsystems. When each of these subsystems is well tested, these tested subsystems can be integrated to produce a robust and reliable full-chip design. Not only does this approach cut risk and rework but time-to-market as well, making the SoC development a more efficient, scalable, and future-ready process.

𝘊𝘰𝘯𝘵𝘢𝘤𝘵 𝘛𝘌𝘚𝘋𝘈 𝘵𝘰 𝘭𝘦𝘢𝘳𝘯 𝘮𝘰𝘳𝘦 𝘢𝘣𝘰𝘶𝘵 𝘩𝘰𝘸 𝘈𝘶𝘵𝘰𝘋𝘝 𝘤𝘢𝘯 𝘴𝘪𝘮𝘱𝘭𝘪𝘧𝘺 𝘺𝘰𝘶𝘳 𝘚𝘰𝘊 𝘷𝘦𝘳𝘪𝘧𝘪𝘤𝘢𝘵𝘪𝘰𝘯.

19/03/2025

🎉 𝗧𝗵𝗮𝗻𝗸 𝗬𝗼𝘂, 𝗣𝗿𝗼𝗳𝗲𝘀𝘀𝗼𝗿! 🎉

A big thank you to Professor from National Tsing Hua University for leading the first session of our USB Study Group at TESDA! Your insights on USB, USB 1.1, and UHCI have provided us with a strong foundation, and we’re excited for the next two sessions.

Looking forward to continuing this learning journey together! 🙌

13/03/2025

🎉 𝗧𝗵𝗮𝗻𝗸 𝗬𝗼𝘂, 𝗣𝗲𝗻𝗻𝘀𝘆𝗹𝘃𝗮𝗻𝗶𝗮 𝗦𝘁𝗮𝘁𝗲 𝗨𝗻𝗶𝘃𝗲𝗿𝘀𝗶𝘁𝘆 🚀

We are happy to have talked with Pennsylvania State University about the future of EDA, SoC verification, and functional safety! Your insights and enthusiasm in terms of innovation in TESDA are inspiring to us.

TESDA will push EDA to its limits to perform efficient SoC verification and even develop next-gen automation solutions. Connecting with leading academic institutions such as Pennsylvania State University fosters collaboration, knowledge sharing, and industry advancement.

Looking forward to future discussions and innovations together! 🤝

11/03/2025

𝗖𝗮𝗹𝗹 𝗳𝗼𝗿 𝗣𝗮𝗽𝗲𝗿𝘀: 𝗗𝗩𝗖𝗼𝗻 𝗧𝗮𝗶𝘄𝗮𝗻 𝟮𝟬𝟮𝟱 – 𝗦𝗵𝗮𝗽𝗲 𝘁𝗵𝗲 𝗙𝘂𝘁𝘂𝗿𝗲 𝗼𝗳 𝗩𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻!

TESDA is calling for all professional industry experts and researchers, together with verification specialists, to submit their papers to DVCon Taiwan 2025. DVCon Taiwan establishes itself as the primary event dedicated to design verification, which serves to exhibit the most recent advancements in SoC verification besides EDA and functional safety methodologies and breakthroughs.

Topics of Interest:
✔️ Verification and Validation
✔️ Design and Verification Reuse / Automation
✔️ Machine Learning and Big Data
✔️ Low-power design and Verification
✔️ Safety-critical / Security-Critical Design and Verification
✔️ Mixed-signal design and Verification

💡 𝗖𝗮𝗹𝗹 𝗳𝗼𝗿 𝗖𝗼𝗻𝘁𝗲𝗻𝘁𝘀
https://dvcontaiwan.org/author-2025/
https://easychair.org/cfp/dvcontaiwan2025
Proceedings of DVCon Taiwan
https://dvcon-proceedings.org/choose-your-location/taiwan/
For more information, visit the DVCon Taiwan Website.

The Design & Verification Conference (DVCon) is the premier conference on the application of languages, tools, methodologies, and standards for the design and verification of electronic systems and integrated circuits.

07/03/2025

𝟴𝟬% 𝗼𝗳 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝘀 𝗪𝗿𝗶𝘁𝗲 𝘁𝗵𝗲𝗶𝗿 𝗧𝗲𝘀𝘁𝗯𝗲𝗻𝗰𝗵𝗲𝘀 𝗠𝗮𝗻𝘂𝗮𝗹𝗹𝘆 - 𝗔𝘂𝘁𝗼𝗺𝗮𝘁𝗶𝗼𝗻 𝗶𝘀 𝘁𝗵𝗲 𝗙𝘂𝘁𝘂𝗿𝗲 𝗳𝗼𝗿 𝗩𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻

Despite the fast developments in tools and methodologies, 𝟴𝟬% 𝗼𝗳 𝗲𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝘀 𝘀𝘁𝗶𝗹𝗹 𝗱𝗲𝗽𝗲𝗻𝗱 𝗼𝗻 𝘁𝗲𝘀𝘁𝗯𝗲𝗻𝗰𝗵𝗲𝘀 𝘄𝗿𝗶𝘁𝘁𝗲𝗻 𝗯𝘆 𝗵𝗮𝗻𝗱. Other than this time-consuming process, manual operation is prone to mistakes, which restricts the performance of verification teams.

Based on 𝗧𝗘𝗦𝗗𝗔 𝘀𝘂𝗿𝘃𝗲𝘆𝘀 (𝗗𝗩𝗖𝗼𝗻 𝗧𝗮𝗶𝘄𝗮𝗻 𝟮𝟬𝟮𝟰), a considerable number of DV engineers also voice frustration regarding the need to manage and keep up manual testbenches. Even with automated solutions being accessible, the uptake is still quite low, as many engineers remain committed to traditional methods due to their past trust and proven reliability.

𝗔𝘂𝘁𝗼𝗗𝗩: 𝗧𝗿𝗮𝗻𝘀𝗳𝗼𝗿𝗺𝗶𝗻𝗴 𝘁𝗵𝗲 𝗪𝗮𝘆 𝗧𝗲𝘀𝘁𝗯𝗲𝗻𝗰𝗵𝗲𝘀 𝗔𝗿𝗲 𝗖𝗿𝗲𝗮𝘁𝗲𝗱
Welcome to AutoDV, an innovative tool for automatic testbench generation that changes how verification is handled by engineers. AutoDV is built with one goal in mind: to facilitate the development of efficient and reusable testbenches to deal with the pain of engineers.

Here's how AutoDV improves efficiency:
✅ 𝗔𝘂𝘁𝗼𝗺𝗮𝘁𝗶𝗰 𝗧𝗲𝘀𝘁𝗯𝗲𝗻𝗰𝗵 𝗚𝗲𝗻𝗲𝗿𝗮𝘁𝗶𝗼𝗻: Rather than spending days creating testbenches, AutoDV produces them for you, greatly reducing the workload.

✅ 𝗦𝗰𝗮𝗹𝗮𝗯𝗶𝗹𝗶𝘁𝘆 𝗮𝗻𝗱 𝗥𝗲𝘂𝘀𝗮𝗯𝗶𝗹𝗶𝘁𝘆: AutoDV-generated testbenches are built to be adaptable and flexible, which makes them easy to utilize for numerous projects or suitable for any kind of design.

✅ 𝗜𝗻𝘁𝗲𝗴𝗿𝗮𝘁𝗶𝗼𝗻 𝘄𝗶𝘁𝗵 𝗟𝗲𝗮𝗱𝗶𝗻𝗴 𝗧𝗼𝗼𝗹𝘀: Combined with our service, AutoDV will integrate into your current verification setup, guaranteeing a smooth transition and quick enhancements in productivity.

✅ 𝗖𝘂𝘁 𝗬𝗼𝘂𝗿 𝗢𝘃𝗲𝗿𝗮𝗹𝗹 𝗩𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻 𝗧𝗶𝗺𝗲: While reducing the testbench creation time, this process also reduces time-to-market as fewer resources are used during the laborious manual processes, which will give engineers time to dedicate their concentration to refining verification approaches and dealing with advanced SoC-level issues.

𝗧𝗵𝗲 𝗙𝘂𝘁𝘂𝗿𝗲 𝗼𝗳 𝗩𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻 𝗵𝗮𝘀 𝗔𝗿𝗿𝗶𝘃𝗲𝗱
The urgency to hit faster project deadlines and deal with more complicated designs makes the requirement for smarter, automated tools increasingly important.

🔜 AutoDV is your ally, helping you cope with these demands and allowing your team to operate with a focus on efficiency, scalability, and precision in verification. It is time to cease utilizing manual testbenches and begin automating your verification process. Be part of the revolution with AutoDV and trim your verification time by 50%.

𝗪𝗮𝗻𝘁 𝘁𝗼 𝗹𝗲𝗮𝗿𝗻 𝗺𝗼𝗿𝗲 𝗼𝗿 𝘀𝗲𝗲 𝗔𝘂𝘁𝗼𝗗𝗩 𝗶𝗻 𝗮𝗰𝘁𝗶𝗼𝗻? Contact us at 𝘀𝗲𝗿𝘃𝗶𝗰𝗲@𝘁𝗲𝘀-𝗱𝗮.𝗰𝗼𝗺 for the free trial and discover how our tool can revolutionize your verification process today!

17/01/2025

🌟 Last night, We just had the pleasure of hosting a wonderful Chinese New Year's Eve Dinner, bringing TESDA together to celebrate the end of a fruitful year and welcome the opportunities of 2025. It was a night filled with laughter, gratitude, and shared aspirations as we reflected on our journey and looked ahead to a brighter future. Here's to innovation, collaboration, and success in the year to come—cheers to the Chinese New Year! 🎉✨

31/12/2024

Learn why verification dominates IC design efforts—click here!

IC Design Verification ensures reliability, catching errors early and reducing costs in complex designs.

24/12/2024

🎄✨ 𝗠𝗲𝗿𝗿𝘆 𝗖𝗵𝗿𝗶𝘀𝘁𝗺𝗮𝘀 𝟮𝟬𝟮𝟰! ✨🎄

This year had its challenges, but your support made all the difference to TESDA. Thank you to everyone who stood by us through it all.
Wishing you a warm and joyful Christmas and a wonderful year ahead! ❤️🎁

11/12/2024

🚀 我們正在尋找 𝗜𝗣/𝗦𝗼𝗖 驗證經理與工程師！
如果您熱衷於電子設計驗證，擁有強大的問題解決能力，並希望在尖端技術中發揮影響力，加入我們的團隊吧！立即申請，成為創新的一部分！

https://lnkd.in/gDQk7eZD

發表於 09:29:16。TESDA 是一家快速成長的初創公司，正在尋找具有 5 年以上經驗的經理或處長和數名數位設計驗證工程師。 作為 TESDA 的設計驗證工程師，您將能夠接觸和驗證來自世界級公司的複雜SoC…在 LinkedIn 查看此職缺與類似...