Cvc Blr

09/06/2015

CVC Pvt Ltd Hiring Fresher’s/Exp as Bcom/BBA Accounts Assistant on 9th June 2015 to 13th June 2015

Company Name: - CVC Pvt Ltd.

Job Position: - Accounts Assistant

Education Qualification: - Bcom or BBA.

Desire Candidate Profile:-

-Candidate should have Ability to do work with any inconvenience
-Candidate must have Good Communications
-Candidate should have Good in accounting Invoicing/billing

Job Role - Handling all Accounting entries, CTC, Payroll, VAT, CST, Service Tax, TDS & Tax Planning for Employees, PT, ESI, PF, Banking, Online Payments & Online Filings, & Other Ares.

Walk-In Location: - Bangalore, Karnataka

Job Location(s):- Bangalore

Experience: - 0 – 2 Years.

Salary: - 8 K to 15 K

Please Carry below documents (mandatory):-

- Updated Resume Copy
- Photo ID Proof (Passport/PAN-Card/Voter-ID/Driving- License/College-ID)
Note: - You can call up given number for any clarifications.
Walk-In Date: - On 9th June 2015 to 13th June 2015.
Walk-In Time: - 10.00 am onwards
Walk-In Venue:-
CVC Pvt Ltd.
422, Vibhu Complex, 2nd Floor, 27th Main,
Sector I, HSR Layout, Bengaluru, Karnataka
Contact number: +91-80-42134156
+91-9620209223

02/04/2015

Free training- Trekking beyond SystemVerilog-UVM with Portable Stimulus
CVC has completed 10 years in business during Dec 2014! Yes, you head it right, we are now a DECADE old, but still very young at heart, high-tech DV company! We want all of YOU, the DV users to be part of this celebrations! Hence, here is our 10th year gift to the DV/UVM community:
Schedule: 4 April 2015, 11.00 to 15.00 (11 AM to 3 PM)
Venue: CVC Office, Bangalore, http://cvcblr.com/?page_id=2
Cost: FREE
Register at: http://goo.gl/forms/8ilFtRolj9

Abstract:
In functional verification, different languages and techniques are used to generate verification stimulus depending on whether a block, subsystem, SoC or system is being verified. When verifying RTL block and subsystem, SystemVerilog is frequently used though ‘e’, SystemC and VHDL are also used. At SoC and system level, embedded software is frequently used to exercise the design. Several challenges result from different languages and techniques being used for block- and subsystem-level verification. It is difficult to leverage block- or subsystem-level test scenarios at SoC and system level. In addition, the embedded software that drives stimulus in SoC and system level environments do not provide support for automated stimulus generation the way that languages such as SystemVerilog do (e.g., constrained random generation) in block- and subsystem-level environments.

In this free, hands-on training you will learn the challenges in current day technology such as SystemVerilog, UVM and learn how Graph Based Verification has been successfully used and emerging as a layer above the conventional SV/UVM and provides portability. Attendees will also have the option of playing with a case study using standard EDA tools.

All Attendees will have the option of buying the best selling SVA book at 25% discount, see: http://verifnews.org/publications/books/
Hurry, limited seating, first-come-first-serve basis
Register at: http://goo.gl/forms/8ilFtRolj9
Agenda:
• Registration
• Speaker introduction
• Presentation
• Networking with high-tea
• Hands-on lab session
Register via: http://goo.gl/forms/8ilFtRolj9

Leads a team of elite, seasoned Verification professionals focused on next generation verification automation and productivity techniques. She has been providing consultancy to leading edge semiconductor houses on various verification challenges for nearly a decade.http://in.linkedin.com/in/ajeetha

26/03/2015

VerifWorks Hiring Freshers as MBA Marketing on 29th Mar 2015

Company Name :- VerifWorks

Job Position :- Marketing

Skills Required :- MBA Marketing.

Education Qualification :- MBA Marketing.

Desire Candidate Profile :-

-Candidate Should have Ability to do work with any inconvenience
-Candidate must have responsible and analysis with his team members
-Candidate should have the leadership quality skills to maintain his team.

Interview Process :-
> Written Test/Online Test
> Technical Round
> H R Round

Walk-In Location :- Bangalore, Karnataka

Job Location(s) :- Bangalore

Experience :- 0 – 2 Years.

Please Carry below documents (mandatory) :-
- Updated Resume Copy
-Photo ID Proof (Passport/PAN-Card/Voter-ID/Driving-License/College-ID)

Note:- You can call up given number for any clarifications.

Walk-In Date :- On 29th March 2015

Walk-In Time :- 10.00 AM onwards

Walk-In Venue :-

VerifWorks(new venture from CVC)
422, Vibhu Complex, 2nd Floor, 27th Main,
Sector I, HSR Layout, Bengaluru, Karnataka
Contact number: +91-80-42134156
+91-9620209223

26/03/2015

VerifWorks Hiring Freshers as Web Developer on 29th Mar 2015

Company Name :- VerifWorks

Job Position :- Web Developer

Job Category :- IT

Skills Required :- Wordpress, JS, CSS,HTML,XML, Adobe flash,DBMS

Job Description :- Design and implement the UI for significant aspects of the product roadmap using primarily AngularJS, BackboneJS, HTML, and CSS. Projects are mainly focused on single-page javascript applications.
Collaborate with other UI and UX professionals, backend engineers, and product managers to realize and deliver these new capabilities to customers.

Participate in all aspects of an Agile/Scrum engineering process from sprint planning to retrospective.
Develop, Participate in Developing Framework & Reusable components.

Establish coding guidelines and provide technical guidance for other team members

Knowledge of SEO, Jquery, Adobe flash etc.

Education Qualification :- BE/B.Tech(EE/EC/CS/IT),MCA

Desire Candidate Profile :-
-Candidate Should have Ability to do work with any inconvenience
-Candidate must have responsible and analysis with his team members
-Candidate should have the leadership quality skills to maintain his team.

Interview Process :-

> Written Test/Online Test
> System Test
> Technical Round
> H R Round

Walk-In Location :- Bangalore, Karnataka

Job Location(s) :- Bangalore

Experience :- 0 – 2 Years.

Please Carry below documents (mandatory) :-

- Updated Resume Copy
-Photo ID Proof (Passport/PAN-Card/Voter-ID/Driving-License/College-ID)

Note:- You can call up given number for any clarifications.

Walk-In Date :- On 29th March 2015

Walk-In Time :- 10.00 AM onwards

Walk-In Venue :-

VerifWorks(new venture from CVC)
422, Vibhu Complex, 2nd Floor, 27th Main,
Sector I, HSR Layout, Bengaluru, Karnataka
Contact number: +91-80-42134156
+91-9620209223

26/03/2015

VerifWorks Hiring Freshers as ASIC Design Verification Engineer on 29th Mar 2015


Company Name :- VerifWorks

Job Position :- ASIC Design Verification Engineer

Skills Required :- Verilog HDL, Python, C, C++.

Job Description :- Perform RTL-level design, including micro-architectural definition, of digital logic used in secure ASIC cores.
Assist with EDA tool-related tasks, such as synthesis, static-timing analysis, logical equivalency checking, and help improve flows and scripts for such tasks.
Knowledge of Verilog HDL, Python, C, C++.

Education Qualification :- BE/B.Tech(EE/EC/CS/IT)

Desire Candidate Profile :-

-Candidate Should have Ability to do work with any inconvenience
-Candidate must have responsible and analysis with his team members
-Candidate should have the leadership quality skills to maintain his team.

Interview Process :-
> Written Test/Online Test
> System Test
> Technical Round
> H R Round

Walk-In Location :- Bangalore, Karnataka
Job Location(s) :- Bangalore

Experience :- 0 – 2 Years.

Please Carry below documents (mandatory) :-
- Updated Resume Copy
-Photo ID Proof (Passport/PAN-Card/Voter-ID/Driving-License/College-ID)

Note:- You can call up given number for any clarifications.

Walk-In Date :- On 29th March 2015

Walk-In Time :- 10.00 AM onwards

Walk-In Venue :-

VerifWorks(new venture from CVC)
422, Vibhu Complex, 2nd Floor, 27th Main,
Sector I, HSR Layout, Bengaluru, Karnataka
Contact number: +91-80-42134156
+91-9620209223

08/03/2015

Celebrating Women's day in style: launching http://womenineda.org - a portal dedicated to Women in our field!

04/03/2015

SystemVerilog quiz: What will be displayed:
// VerifLabs www.veriflabs.com a CVC venture
// Small SystemVerilog design code to demo the enum init in SV
typedef enum logic [7:0]
{
VAL_22 = 22,
VAL_23, VAL_24
} val_t;
module m;
val_t v0;
initial begin
#10;
$display ("VerifLabs: Enum val by default: %0d string: %s", v0, v0.name());
end
endmodule : m

ASIC & FPGA learning through hands-on experimentation

04/03/2015

Our DVEnc product introduction as a slideshow

01/03/2015

TeamCVC photo from 2013-14, most of them joined us as trainee for 6-months, then worked at our customer projects (onsite/offsite) and now settled in MNCs, design services etc.

24/02/2015

Career path for successful VLSI engineer with CVC ventures - do you want to be part of this journey too? If yes, contact us via www.cvcblr.com

24/02/2015

What inspired you to become an engineer?
National Engineering Week is February 22-28

See our CTO, Srini's thoughts:

https://www.aldec.com/en/company/blog/89--what-inspired-you-to-become-an-engineer

This week, February 22-28, we celebrate National Engineers Week in the US to recognize the contributions to society that engineers make.