07/08/2025
NEO Semiconductor Unveils World's First X-HBM Architecture, Marking a Major Leap in AI Memory Technology
NEO Semiconductor, a leader in memory technology innovation, has announced the launch of the world’s first Extreme High Bandwidth Memory (X-HBM) architecture—setting a new benchmark for AI and high-performance computing applications.
Specifically designed to meet the rapidly escalating demands of generative AI and HPC workloads, X-HBM features a groundbreaking 32K-bit data bus and delivers up to 512 Gbps per die—far surpassing the capabilities of current High Bandwidth Memory (HBM) solutions.
“X-HBM is not just an incremental improvement—it's a revolutionary breakthrough,” said Andy Xu, founder and CEO of NEO Semiconductor. “Offering 16 times the bandwidth or 10 times the density of today’s memory technologies, X-HBM paves the way for AI chipmakers to unlock next-gen performance well ahead of industry timelines. It’s a transformative advancement for building AI infrastructure, optimizing energy efficiency, and scaling AI across sectors.”
Built on NEO’s proprietary 3D X-DRAM architecture, X-HBM overcomes longstanding limitations in memory bandwidth and density. By comparison, HBM5, still under development and projected for release around 2030, will support only a 4K-bit data bus and 40 Gbps per die. A recent study by the Korea Advanced Institute of Science and Technology (KAIST) projects that even HBM8, expected by 2040, will be limited to 16K-bit buses and 80 Gbps per die.
With X-HBM’s 32K-bit bus and 512 Gbps per die, NEO Semiconductor offers a powerful alternative that allows AI hardware designers to bypass many of the performance bottlenecks tied to traditional HBM architectures.
