20/10/2026
As mobile communication systems move toward 6G, improving error correction decoders is no longer just an information theoretic problem. One challenge is the increasing impact on the cost of moving data on silicon. At the 2026 IEEE Nordic Circuits and Systems Conference (NorCAS) in Tampere, Finland, Oliver Griebel presented our joint research with Prof. Dr.-Ing. Norbert Wehn who is leading the Division of Microelectronic Systems Design (EMS) at RPTU Kaiserslautern-Landau:
"𝗝𝗼𝗶𝗻𝘁 𝗘𝗻𝘁𝗿𝗼𝗽𝘆-𝗤𝘂𝗮𝗻𝘁𝗶𝘇𝗮𝘁𝗶𝗼𝗻 𝗢𝗽𝘁𝗶𝗺𝗶𝘇𝗮𝘁𝗶𝗼𝗻 𝗼𝗳 𝗟𝗗𝗣𝗖 𝗗𝗲𝗰𝗼𝗱𝗲𝗿𝘀 𝘂𝗻𝗱𝗲𝗿 𝗦𝗶𝗹𝗶𝗰𝗼𝗻 𝗜𝗺𝗽𝗹𝗲𝗺𝗲𝗻𝘁𝗮𝘁𝗶𝗼𝗻 𝗖𝗼𝗻𝘀𝘁𝗿𝗮𝗶𝗻𝘁𝘀."
The work investigates a key question for high-throughput LDPC decoders:
𝘉𝘺 𝘩𝘰𝘸 𝘮𝘶𝘤𝘩 𝘥𝘰𝘦𝘴 𝘥𝘢𝘵𝘢 𝘮𝘰𝘷𝘦𝘮𝘦𝘯𝘵 𝘪𝘮𝘱𝘢𝘤𝘵 𝘵𝘩𝘦 𝘪𝘮𝘱𝘭𝘦𝘮𝘦𝘯𝘵𝘢𝘵𝘪𝘰𝘯 𝘤𝘰𝘮𝘱𝘭𝘦𝘹𝘪𝘵𝘺 𝘰𝘧 𝘓𝘋𝘗𝘊 𝘥𝘦𝘤𝘰𝘥𝘦𝘳𝘴 𝘪𝘯 𝘢𝘥𝘷𝘢𝘯𝘤𝘦𝘥 𝘵𝘦𝘤𝘩𝘯𝘰𝘭𝘰𝘨𝘺 𝘯𝘰𝘥𝘦𝘴?
Our research analyzes the interaction between code structure and message quantization on LDPC decoder implementations across different technology nodes. The results show that implementation-aware optimization can significantly improve energy efficiency, while conventional technology scaling alone delivers only limited gains.
Future FEC architectures require joint optimization across code, decoding algorithm, and decoder architecture. Treating each domain independently leaves efficiency on the table.
We enjoyed discussing these findings with researchers and industry experts at NorCAS 2026.
