深圳市信云达电子科技有限公司 Shenzhen XYD ET LTD

29/05/2026

When designing high-frequency PCBs (above 10 GHz), one factor often overlooked is the copper foil profile. Not all copper is equal. Standard electrodeposited (ED) copper has a rough drum side with peaks averaging 5–10 µm. That roughness increases conductor losses through the "skin effect," where high-frequency currents crowd the surface. The rougher the interface, the longer the current path and the greater the insertion loss.

In contrast, **VLP (very low profile)** or **RTF (reverse treated foil)** copper reduces roughness to under 2 µm. This directly improves signal integrity by minimizing attenuation. However, switching to smoother copper demands tighter control over laminate adhesion. Manufacturers must balance peel strength against electrical performance—typically verified through IPC-4101 laminate qualification.

Another critical parameter is **Dk (dielectric constant)** and **Df (dissipation factor)** stability across frequency. At millimeter-wave designs, even a 0.1 variation in Dk can shift impedance by several ohms. That’s why material selection should include measured data at your specific operating frequency, not just vendor datasheet values.

On the fabrication side, **impedance control** becomes more sensitive with low-loss materials. Etch compensation must be recalibrated because smoother copper etches faster than rough copper, widening trace widths unintentionally. A common pitfall is assuming standard compensation factors apply—they don't.

If your design passes 28 Gbps or higher, specify foil type and laminate tolerance in your fabrication notes. Many PCB shops default to standard ED copper unless told otherwise. Ask for VLP or RTF and confirm Dk/Df testing results.

For dependable PCB/PCBA ex*****on, visit pcbdog.com.

PCB PCBA one stop solution www.pcbdog.com [email protected]

29/05/2026

Challenge for PCB Design Engineers: Can you find your application field in this map?
Many people still think PCBs are mainly used in consumer electronics.
But today, PCBs are everywhere:
Automotive electronics.
AI computing servers.
Optical communication modules.
High-voltage power transmission.
Industrial automation.
Medical electronics.
Aerospace.
IoT.
Smart devices.
From traditional electronics to high-speed computing and energy systems, PCB technology is becoming the foundation of almost every critical industry.
For PCB design engineers, the real question is not only:
“Can this board be manufactured?”
But also:
Can it handle high-speed signals?
Can it manage heat?
Can it survive vibration, humidity, and long-term operation?
Can it meet the reliability requirement of the real application?
At PCBDOG, we focus on high-reliability PCB and PCBA manufacturing for demanding applications — from prototype to production.
Take a closer look at this map.
Did we cover your industry?
Or is there one important application field we missed?
Let us know in the comments.
🌐 www.pcbdog.com
📩 [email protected]

28/05/2026

Today’s insight targets a subtle but critical aspect of high-speed PCB design: via stitching for EMI suppression.

In multi-layer boards operating above 1 GHz, ground return paths are easily disrupted by signal transitions between layers. Improper via placement creates unwanted inductance and common-mode radiation. Via stitching—placing small ground vias along the edges or near high-speed traces—provides a low-impedance path for return currents and reduces loop area.

But ex*****on matters. A single ground via at a transition point is often insufficient. You need a fence or a grid of ground vias spaced at less than λ/20 of the highest harmonic frequency. For a 10 GHz signal, that means via pitch under 1.5 mm. Use microvias in HDI designs to achieve this density without drilling through the entire stackup.

Also consider the dielectric material’s dielectric constant (Dk) and dissipation factor (Df). FR-4 is unsuitable for high-frequency via stitching due to its high Df above 1 GHz. Low-loss laminates (e.g., Rogers 4350B) maintain signal integrity while supporting tight via spacing. Always verify via aspect ratio and plating thickness—thin copper can crack under thermal stress, breaking the stitching fence.

One common mistake: leaving large copper pours unstitched near connectors. This turns the copper into an unintentional radiator. Stitch every 5–10 mm around the perimeter of ground planes, especially adjacent to high-speed differential pairs. Use thermal relief spokes sparingly on these vias to maintain DC connectivity while avoiding soldering defects.

Another nuance: blind vias can be used for internal layer stitching without breaking the outer ground plane. This preserves the shielding integrity of the outer layers.

For dependable PCB/PCBA ex*****on, visit pcbdog.com.

PCB PCBA one stop solution www.pcbdog.com [email protected]

28/05/2026

For years, the electronics industry focused on one direction: make chips smaller.
But Huawei’s Tau (τ) Scaling Law brings a new perspective:
the next battle is not only about geometry — it is about time.
When signal propagation delay becomes a bottleneck, PCB technology must evolve together with chips:
✅ Higher-density interconnect
✅ Finer traces
✅ Microvias and via-in-pad
✅ Low-loss high-frequency materials
✅ Better power delivery and thermal design
✅ Higher reliability for AI, automotive, telecom, and data centers
A PCB is no longer just a carrier for components.
It is becoming a critical part of system performance.
At PCBDOG, we believe the future of PCB manufacturing will be defined by one question:
Can your board support the speed of your system?

27/05/2026

**Via-in-Pad: Solving Density Without Sacrificing Reliability**

As PCB designs shrink to meet the demands of handheld and IoT devices, via-in-pad (VIP) has moved from niche to necessity. But placing a via directly under an SMD pad introduces risks—solder voids, wicking, and mechanical stress.

The solution lies in **plugged vias**. By filling the via barrel with a non-conductive (or conductive) epoxy and then capping it with copper plating, you create a flat, solderable surface. This prevents solder from flowing into the barrel and eliminates voids under the component.

Two common approaches:
- **Non-conductive plugging** (epoxy fill, copper cap) – cost-effective for most designs.
- **Conductive plugging** (copper paste) – used for thermal management or when the via must carry current through the pad.

Surface finish matters. **ENIG** over the capped pad provides a planar, wire-bondable surface. Without proper plugging, ENIG can cause “black pad” or brittle intermetallics from uneven plating.

Key manufacturing checks:
- Plug depth consistency (must fill the barrel completely).
- Cap plating thickness (typically 10–15 µm).
- Flatness after planarization (< 0.1 mm coplanarity per IPC-6012).

For high-reliability applications (automotive, medical), specify **via fill qualification** in the fabrication notes. Also watch out for stacked microvias—plugging a stack is more complex and requires tighter aspect ratio control.

Using via-in-pad with proper plugging allows designers to shrink fan-out area, reduce layer count, and improve signal integrity. It’s a process that demands precision, but when executed correctly, it delivers the density your design needs without field failures.

For dependable PCB/PCBA ex*****on, visit pcbdog.com.

PCB PCBA one stop solution www.pcbdog.com [email protected]

27/05/2026

Why can PCB prices differ by 20–30% even with the same drawing?

Because the drawing only defines the design.
It does not fully define the manufacturing standard.

A lower quotation may look attractive, but hidden differences can exist in:

• Laminate brand and material stability
• Copper thickness control
• Hole copper plating reliability
• Surface finish and process consistency
• Flatness and warpage control
• Testing coverage
• DFM and engineering support

For example, a low-quality PCB may use KB or unbranded laminate, with higher risk of warpage, unstable material performance, and internal copper ion migration under heat and humidity.

A high-reliability PCB should use stable branded materials such as SHENGYI or ITEQ, controlled copper thickness, reliable via plating, better process control, and stronger testing standards.

At PCBDOG, we do not compete only on the lowest price.

We compete on reliability, consistency, and long-term product performance.

Because for industrial electronics, communication devices, drones, automotive, medical, and high-reliability applications, PCB failure is never cheap.

Lower price is not always the lowest total cost.

A good PCB saves cost after delivery.

🌐 www.pcbdog.com
📩 [email protected]

26/05/2026

**Date: 2026-05-26**

Via-in-pad with copper filling is often specified for high-density designs, yet many teams treat it as a simple process variation. It is not. Ex*****on errors here cause pad lift, voiding, and reliability failures in thermal cycling.

The key challenge lies in filling the via with copper without leaving a dimple or protrusion. Subsequent planarization must yield a flat surface. Even a 10-micron depth variation can trap solder paste, leading to head-in-pillow defects during reflow.

**Process realities to audit:**

- **Copper fill plating:** After drilling, PTH plating builds the barrel, then secondary plating fills the via. Rectifier waveform and solution composition control uniformity. Poor waveform produces a concave surface, forcing an aggressive planarization pass. That pass can reduce finished copper thickness below spec.

- **Solder mask design over filled vias:** A proper finish uses LPI or dry-film solder mask with an opening larger than the filled via. If the mask overlaps the copper fill edge, adhesive outgassing during reflow creates voids. For BGAs or QFNs, specify mask-defined pads with a 50–70 µm clearance from the via center.

- **Surface finish compatibility:** Immersion silver or ENIG over copper-filled vias is standard, but nickel thickness must be controlled. Excess nickel can embrittle the via-column interface, especially if the fill copper contains organic contaminants from the plating bath.

**Inspection criteria:**

- X-ray for internal voids >25% of via diameter.
- Cross-section for flatness: target ≤15 µm deviation from pad surface.
- Thermal stress at 288°C for 10 seconds — any blistering or delamination stops production.

A common mistake is assuming that filling material and plating copper have identical CTE. They do not. Use a low-CTE fill chemistry (

26/05/2026

A great PCB & PCBA manufacturer does more than just build your board.
For advanced electronics, the real value is hidden in the details:
✅ High-frequency and low-loss communication performance
✅ Stable power distribution and signal integrity
✅ Better thermal management for high-power applications
✅ Reliable assembly for demanding environments
✅ Manufacturing experience for drones, aerospace, industrial control, and communication devices
At PCBDOG, we focus on engineering-driven PCB and PCBA manufacturing — from DFM review, material selection, impedance control, SMT assembly, X-ray inspection, to functional testing.
Because for high-reliability products, “it can be made” is not enough.
It must be stable. It must be reliable. It must perform in the real application.
Looking for a reliable PCB & PCBA manufacturing partner for your next high-performance project? Let’s talk.
🌐 www.pcbdog.com 📩 [email protected]

26/05/2026

26/05/2026

A great PCB & PCBA manufacturer does more than just build your board.
For advanced electronics, the real value is hidden in the details:
✅ High-frequency and low-loss communication performance
✅ Stable power distribution and signal integrity
✅ Better thermal management for high-power applications
✅ Reliable assembly for demanding environments
✅ Manufacturing experience for drones, aerospace, industrial control, and communication devices
At PCBDOG, we focus on engineering-driven PCB and PCBA manufacturing — from DFM review, material selection, impedance control, SMT assembly, X-ray inspection, to functional testing.
Because for high-reliability products, “it can be made” is not enough.
It must be stable. It must be reliable. It must perform in the real application.
Looking for a reliable PCB & PCBA manufacturing partner for your next high-performance project? Let’s talk.
🌐 www.pcbdog.com 📩 [email protected]

High-frequency PCB & PCBA manufacturer in China specializing in RF, radar and high-speed multilayer boards. One-stop service from PCB fabrication to assembly with HDI, rigid-flex and turnkey solutions. Get fast quote & DFM support.

25/05/2026

As signal speeds climb into the millimeter-wave range, the stub length left by through-hole vias becomes a critical performance limiter. Back-drilling — the secondary controlled-depth removal of the unused barrel portion — is the most effective countermeasure, but it comes with strict manufacturing tolerances that many designers underestimate.

A back-drilled via's residual stub must be held well under 10 mils to avoid resonance effects above 10 GHz. Achieving that consistently requires tight control over drill depth accuracy (±2 mils typically), precise laminate thickness registration, and a cleanly tooled entry material. If the drill hits the target pad, you risk shorting the inner-layer connection. If it stops too early, the stub remains and degrades insertion loss.

The process sensitivity increases with aspect ratio. For a 20-layer board with 0.35 mm finished hole diameter, back-drilling from the top side to a depth of 1.0 mm demands a drill geometry that maintains coaxial alignment across multiple stack-ups. Many fabricators limit back-drilling depth to avoid damaging adjacent cores. We evaluate drill wander using X-ray cross-sectioning for every new stack-up design.

Two practical rules we follow:

1. Specify the minimum allowable back-drilled depth, not just the maximum stub length. This gives the manufacturer flexibility to adjust parameters per panel.

2. Always include a defined target layer—typically one internal copper plane—to serve as the depth stop. Without it, the drill depth becomes a guess based solely on the Z-axis stack-up.

Back-drilling adds cost and may complicate plating on the exposed barrel if not sealed immediately. But for designs using high-speed protocols like PCIe Gen 6 or 112 Gbps PAM4, it is non-negotiable.

For dependable PCB/PCBA ex*****on, visit pcbdog.com.

PCB PCBA one stop solution www.pcbdog.com [email protected]