eASIC® is a fabless semiconductor company offering breakthrough eASIC Platforms that significantly reduce the overall cost of ownership and time to production of customized silicon devices. Employing a unique and patented technology for customization using a single via, eASIC enables customers to develop custom silicon with low up-front costs, and deliver tested prototypes in as little as 5 weeks
from tape out. While the customization technology is innovative and protected by broad patents, the design implementation and device fabrication are performed using conventional electronic design flow and standard manufacturing processes. Disruption Through Technology
The logic market for custom chips has traditionally been dominated by two technologies, namely FPGAs and standard cell ASICs. FPGAs provide very low start-up costs making them the platform of choice for many prototyping applications. SRAM FPGAs in particular, have gained the lion’s share of the overall market. Packed with SRAM cells and abundant routing, FPGAs provide the designer with a reprogrammable architecture that is well suited for development. However, the silicon overhead required for reprogrammability can be as much as 80% of the overall die size, thereby adding significantly to the device cost and power consumption of the device and sacrificing performances. Once prototyping is completed designers have sought to move to lower cost solutions such as standard cell ASICs. Standard cell ASICs utilize two-input NAND gates as the fundamental building blocks. This, coupled with the ability for designers to customize all mask layers makes standard cell the preferred solution for very high volume applications. However, a number of factors have contributed to the rapid demise in the number of standard cell ASIC design starts over the last 10 years. These factors include: exponentially rising mask costs, high-priced EDA tools, lengthy design cycles, long manufacturing cycles, expensive sub-micron design expertise and unpredictable ROI. These factors have combined to limit the use of standard cells for all but the highest volume market applications. eASIC’s innovative architecture delivers a new generation of eASIC Platform technology that makes silicon customization affordable for the masses. Replacing SRAM based routing with a scheme that utilizes a single via, significant die size reduction can be achieved compared to comparable density FPGAs. This in turn results in significant cost and power savings for designers. The single via approach also significantly reduces up-front development cost, design and manufacturing time compared to standard cell ASICs. A single via layer requires much less time to validate and manufacture than an all layer standard cell design. With eASIC, designers also need not be concerned with many arduous tasks such as test insertion, clock balancing, ATPG, LVS/DRC, signal integrity analysis, power droop mesh design, tasks that are mandatory for standard cell ASIC design. eASIC platforms are being successfully used by customers all over the world in applications that span from wireless infrastructure to consumer handheld devices. eASIC Platforms are fast becoming the preferred silicon customization solution for production volumes up to approximately one million units per year.
